1. Field of the Invention
The Present invention relates to flash-based field-programmable gate array (FPGA) integrated circuits. More particularly, the present invention relates to a radiation-tolerant flash-based field-programmable gate array.
2. The Prior Art
Flash-based field-programmable gate array integrated circuits are known in the art. Such FPGAs use a flash switch including a floating gate memory transistor that shares a floating gate with a switch transistor that is used to make programmable connections between circuit nodes in the FPGA device. Both the memory transistor and the switch transistor are typically n-channel transistors. Radiation due to heavy ions will damage the silicon dioxide either above or below the floating gate in a flash switch in a FPGA device. Over time in a radiation environment, an increasing portion of the flash switches in the FPGA will be affected.
A heavy ion passing through the silicon dioxide either above or below the floating gate can dislocate atoms from their nominal location in the lattice structure making up the oxide. These irregularities can become charge traps that would not exist in undamaged oxide. The presence of these unwanted charge traps can allow electrons to slowly migrate from the floating gate by hopping from charge trap to charge trap. This will cause the flash switch to change state, either from an on state to an off state or vice versa. This state change cannot be tolerated since it will cause unpredictable behavior in the programmed circuit that is configured in the FPGA.
Referring now to FIG. 1A, a schematic diagram shows a portion of a prior-art memory cell illustrating its use in an FPGA to allow a programmable a connection between two circuit elements and demonstrates one of the problems inherent in the prior art. Circuit 10 and circuit 12 are disposed in an FPGA integrated circuit. Switch transistor 14 is coupled between circuit 10 and circuit 12 by means of interconnects 11 and 13 respectively. If the memory transistor (not shown) with which it shares a floating gate is erased, switch transistor 14 will be turned on and a connection will be made between circuit 10 and circuit 12. If, however, the memory transistor with which it shares a floating gate is programmed, switch transistor 14 will not be turned on and a connection will not be made between circuit 10 and circuit 12.
This circuit arrangement is satisfactory unless a radiation event occurs with respect to the floating gate shared by switch transistor 14 and the memory transistor with which it is associated. In such a case, the radiation can act to program the floating gate that was intended to remain erased, or erase the floating gate that was intended to remain programmed. The result is either that an unintended connection is made between circuit 10 and circuit 12 or an intended connection between circuit 10 and 12 is severed. In either case, the operation of the circuit programmed into the FPGA is compromised and the result is unpredictable, since there is no way to know which floating gate will be hit by a radiation event and whether the event will act to program or erase the affected floating gate.
Floating gate transistors are not the only type of non-volatile flash transistor known in the art. Other flash technologies like, for example, SONOS and nano-crystal are also known. The common characteristic amongst these technologies is that each has a mechanism for deliberately storing electrical charge between the external gate node and the channel region of the transistor and for selectively adding or removing charge from that storage mechanism to control the transistor threshold voltage. The stored charges remain when the part is powered down allowing the programming information to remain, hence the non-volatile nomenclature.
In floating gate transistors, the control charges on the floating gate are mobile within the confines of the floating gate, while in SONOS or nano-crystal technologies the control charges are not mobile. In embodiments where a memory transistor and a switch transistor share a floating gate, the ability of stored charges to move freely between the memory and switch transistors is essential and the flash technologies with immobile control charges would not be suitable in such embodiments. In other embodiments, all flash technologies are suitable.
Other sorts of transistors are present on an FPGA employing any non-volatile technology. For purposes of this specification, these transistors will be called “standard transistors” meaning a normal MOSFET transistor, either n-channel or p-channel, as is well known in the art, that has no deliberately fabricated charge storage mechanism between the gate and channel. Thus standard transistors cannot have charge selectively added or removed to deliberately control the transistor threshold voltage. In any particular application or embodiment, a standard transistor may be, for example, a low-voltage thin-gate-oxide logic transistor, a middle-voltage medium-gate-oxide I/O transistor, or a high-voltage thick-gate-oxide transistor, all of which are well known in the art and typically present in a flash-based FPGA, as a matter of design choice. Standard transistors may be either n-channel or p-channel and either type may be doped to have a positive or negative threshold voltage, though typically n-channel transistors have positive threshold voltages and p-channel transistors have negative threshold voltages. As is known in the art, n-channel transistors conduct current by means of negatively charged electrons when turned on by applying a higher voltage to the gate terminal than in the off state, while p-channel transistors conduct current by means of positively charged holes when turned on by applying a lower voltage to the gate terminal than in the off state. In some places in this specification a further qualified phrase like, for example, “a standard switch transistor” is used meaning a switch made from a standard transistor.
Also known in the art are FPGAs built exclusively of standard transistors. Such FPGAs necessarily use volatile memory cells like, for example, Static Random Access Memory (SRAM) cells, that must be initialized to hold their programming information. FIG. 5A illustrates an SRAM memory cell 180 of a type that is well known in the art that can be used in such an FPGA. Memory cell 180 comprises cross-coupled inverters 181 and 182, pass transistors 183 and 184, row access line 185 which is coupled to the gates of pass transistors 183 and 184, output node 186 which is coupled to the source of pass transistor 184, the input of inverter 182 and the output of inverter 181, and complimentary node 187 which is coupled to the source of pass transistor 183, the output of inverter 182 and the input of inverter 181. The drains of pass transistors 183 and 184 are coupled to a pair of complimentary column access lines not shown. Cross-coupled inverters 181 and 182 form a latch capable of storing one bit of binary data. Pass transistors 183 and 184 provide read or write access to the latch when row access line 185 is driven to logic-1. Output node 186 is coupled to a circuit or device in the FPGA that needs to be controlled like, for example, a standard switch transistor. Complimentary node 187 could also be brought out, alternatively or additionally, to be used to control FPGA circuitry or devices.
Different radiation effects resulting in different failure mechanisms come into play in an SRAM based FPGA. While heavy ions can damage the gate oxide of a standard transistor, unless the damage is extremely severe (to the point where the gate gets shorted to the silicon substrate underneath the gate) the result is an undesirable but typically tolerable amount of gate leakage. While gate leakage is catastrophic for a floating gate transistor since the floating gate is no longer isolated and charge can leak off changing the programming state, a standard transistor with a moderate amount of gate leakage will still continue to function like a standard transistor.
In SRAM based FPGAs, the major concern for the programming memory cells is Single Event Upset (SEU) which can be caused not only by heavy ions but also by much lighter charged particles like, for example, electrons, protons and helium nuclei (alpha particles). When a charged particle passes through a doped semiconductor region, it ionizes the atoms it encounters leaving a temporary surplus of unwanted hole and electron pairs in its wake. If the particle crosses a boundary between differently doped regions (a p/n junction) that are operating at different voltages, the surplus carries have the effect of creating a temporary short between the two regions that are normally isolated by the p/n junction and current can flow from one region to the other. If one of the regions is the drain node of one of the transistors in either inverter 181 or inverter 182 in memory cell 180, this temporary short can inject enough charge into node 186 or 187 that the memory cell 180 flips to the opposite logic value.
In FIG. 5B a Triple Module Redundancy (TMR) circuit known in the art that is typically used to provide radiation hardness by mitigating SEUs for latches such as memory cell 180 is shown generally by reference number 190. TMR circuit 190 comprises three memory cells 180. The outputs of memory cells 180 are coupled to the three inputs of a voting gate 191, that has an output node 192. Output node 192 is coupled to a circuit or device in the FPGA like, for example, a standard switch transistor, in order to control it. The voting gate, which is also known as a Majority-of-three gate or MAJ3, implements the Boolean function MAJ3(a, b, c)=(a AND b) OR (a AND c) OR (b AND c). When any two or all three inputs are driven to logic-1, the output of the voting gate 191 will be driven to logic-1. Similarly, when any two or all three inputs are driven to logic-0, the output of the voting gate 191 will be driven to logic-0. All three memory cells 180 are all programmed to the same logical value. If the logical value of one of the memory cells 180 is flipped due to SEU, the other two cells 180 and the voting gate 191 will ensure that the output node 192 remains at the correct logical value. Typically, scrubbing (repeatedly rewriting some or all of the programming data in the SRAM memory cells 180) is necessary for SRAM based FPGAs to operate reliably in a radiation environment—even with the use of TMR circuits since the TMR circuit 190 doesn't prevent SEUs from occurring but rather creates a delay in time between the first SEU affecting one of the SRAM bits 180 and a second SEU affecting a second one of the SRAM bits 180.